Interrupt register
| TX_TRIGGER | Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL. |
| TX_NOT_FULL | TX FIFO is not full. |
| TX_EMPTY | TX FIFO is empty; i.e. it has 0 entries. |
| TX_OVERFLOW | Attempt to write to a full TX FIFO. |
| TX_UNDERFLOW | Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is ‘1’. |
| TX_WD | Triggers (sets to ‘1’) when the Tx watchdog event occurs. |
| RX_TRIGGER | More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL. |
| RX_NOT_EMPTY | RX FIFO is not empty. |
| RX_FULL | RX FIFO is full. |
| RX_OVERFLOW | Attempt to write to a full RX FIFO. |
| RX_UNDERFLOW | Attempt to read from an empty RX FIFO. |
| RX_WD | Triggers (sets to ‘1’) when the Rx watchdog event occurs. |